Apparatus and method for the characterization of analog-to-digital converters

ABSTRACT

A method and apparatus for characterizing an A/D converter are provided. The A/D converter is configured to convert an input signal into a digital output signal. The method and apparatus may provide: applying an input signal to the A/D converter that in a first phase at least includes a gradient of a rising exponential function with Euler&#39;s number as the base, and in a further phase has a profile of a falling exponential function with Euler&#39;s number as the base, integrating a digital output signal associated with the A/D converter during the first phase to provide a first sum, integrating the digital output signal associated with the A/D converter during the further phase to provide a second sum, and calculating from the first sum and the second sum at least a gain error of the A/D converter and/or a zero point error of the A/D converter.

RELATED APPLICATIONS

This application claims priority of German patent application number 102013 007 903.9. The entire contents of the German patent application arehereby incorporated herein by reference.

BACKGROUND

The subject matter of this application generally relates to an apparatusand method for calculating parameters associated with analog-to-digital(A/D) converters.

Complex system-on-chip (SoC) components, such as microcontrollers forautomotive applications, include a plurality of A/D converters. It isdesirable that their functionality be checked during a production test.It may be advantageous that in the future, in addition, a test can becarried out during normal operation of the vehicle in the installedstate. Methods are known in which a linearly rising signal is applied toone input of a test A/D converter. From the comparison of the outputsignal of the A/D converter with expected values it is possible todetermine offset errors (also called zero point errors) and gain errorsassociated with the A/D converter.

SUMMARY

Therefore, it may be desirable to provide a method that requires aminimum effort for the test. It may be particularly desirable to providea test method that may be provided or loaded into a block to be tested(device under test, DUT).

In one embodiment, a method of characterizing an A/D converter isprovided. The A/D converter is configured to convert an input signalinto a digital output signal. The method may comprise: applying an inputsignal to the A/D converter that in a first phase at least includes agradient of a rising exponential function with Euler's number as thebase, and in a further phase has a profile of a falling exponentialfunction with Euler's number as the base, integrating a digital outputsignal associated with the A/D converter during the first phase toprovide a first sum, integrating the digital output signal associatedwith the A/D converter during the further phase to provide a second sum,and calculating from the first sum and the second sum at least a gainerror of the A/D converter and/or a zero point error of the A/Dconverter.

In another embodiment, an electronic circuit is provided to characterizeA/D converter. The A/D converter is capable of converting an analoginput signal to a digital output signal. The electronic circuit mayinclude a generator for providing an input signal. The input signal tothe A/D converter may in a first phase at least include a gradient of arising exponential function with Euler's number as the base, and in afurther phase, the input signal may include a profile of a fallingexponential function with Euler's number as the base. The electroniccircuit may further include an integrator to integrate a digital outputsignal associated with the A/D converter during the first phase toprovide a first sum, the integrator to further integrate the digitaloutput signal associated with the A/D converter during the further phaseto provide a second sum. Furthermore, the electronic circuit may includea calculation unit for calculating from the first sum and the second sumat least a gain error of the A/D converter and/or a zero point error ofthe A/D converter.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are shown and illustrated with reference to the drawings.The drawings serve to illustrate the basic principle, so that onlyaspects necessary for understanding the basic principle are illustrated.The drawings are not to scale. In the drawings the same referencecharacters denote like features.

FIG. 1 illustrates an exemplary schematic diagram of a circuit fordetermining zero point errors and/or gain errors of an A/D converterunder test;

FIG. 2 illustrates a curve associated with output voltages of an A/Dconverter; and

FIG. 3 illustrates an exemplary embodiment of the circuit illustrated inFIG. 1.

DETAILED DESCRIPTION

A device 1 is illustrated in FIG. 1. The device 1 is configured to testan A/D converter 4. The device 1 may include, in addition to the A/Dconverter 4, an oscillator to, a function generator 3, a detectorcircuit 5 and a control circuit 7. The various elements of the device 1may be monolithically integrated as an integrated circuit 6. In oneembodiment, all the elements of the device 1, except for the A/Dconverter 4, are monolithically integrated as an integrated circuit.That is, the A/D converter 4 may be implemented as a separate componentfrom the other elements of the device 1. In yet another embodiment, oneor more elements of the device 1 is a separate component.

As is illustrated in FIG. 1, the A/D converter 4 includes inputs E andC. The E input is to receive data. The C input is to receive a clocksignal (CLK). The A/D converter 4 also includes an output Q. The E inputof the A/D converter 4 is coupled to an input IN of the integratedcircuit 6. The oscillator 2 outputs the clock signal to the input C ofthe A/D converter 4. The function generator 3 provides an analog signal(u_(in)) at an output thereof. The output of the function generator 3 iscoupled to the input E of the A/D converter 4. The output Q of the A/Dconverter 4 is coupled to an input E5 of the detector circuit 5. Inaddition, the output Q of the A/D converter 4 is coupled to an input E6of the control circuit 7.

The oscillator 2 generates the clock signal during both a normaloperation as well as in a test operation. The clock signal is receivedby the A/D converter 4 at the input C. The clock signal received by theA/D converter 4 is used by the converter 4 as a sampling clock signal.The A/D converter 4 converts analog signals received at the input E todigital signals in accordance with the sampling rate of the samplingclock signal received thereby. The digital signals are provided on theoutput Q.

As part of a normal operation of the integrated circuit 6, the circuit 6receives an analog signal which is converted by the A/D converter 4 intoa digital signal OUT. The function generator 3 switches its output to ahigh impedance level. The digital signal OUT is received by the controlcircuit 7 and is used to generate a control signal (control) that isoutput by the integrated circuit 6. The control signal may be used tocontrol an actuator of a controller unit, which is not illustrated inFIG. 1. As an alternative embodiment, as is shown by the dashed linecoupled to the output Q of the A/D converter 4, the digital signal OUTmay bypass the control circuit 7 and therefore be provided directly toan output of the integrated circuit 6.

As part of a test operation of the integrated circuit 6, the signalu_(in) is provided by the function generator 3. In this particularembodiment of operation, a signal is not provided on the input IN of theintegrated circuit 6. Therefore, the signal u_(in) received at the inputE of the A/D converter 4. The signal u_(in) is converted from an analogform to a digital form by the A/D converter 4 and output as the digitalsignal OUT output Q. The digital signal OUT is received by the detectorcircuit 5, which generates in accordance with the digital signal OUT azero point error signal a₀ and a gain error signal g₀ u₀. The values ofa₀ and g₀ u₀ can be output to control circuits external to theintegrated circuit 6, which generate an error message if the values a₀and/or g₀ u₀ are outside a predetermined range. In an alternative, thevalues may be used to calibrate the ATD converter 4. The evaluationcircuit 5 also receives the clock signal CLK at a clock input C of theevaluation circuit 5.

FIG. 2 shows the variation of an output voltage Vout of an A/Dconverter, such as the A/D converter 4, in response to the input voltageVin of the A/D converter. In all graphs shown in FIG. 2 provide asimplified representation of various signals; quantization is not shown.That is, the curves are drawn with straight lines, whereas outputvoltages of actual A/D converters generally have a stepped response, ornon-flat profile. In the figure, a curve is shown u_(ideal) that startsat the origin and has a linear trend. A u_(par) curve starts, with aninput voltage Vin of zero volts, at a voltage a₀, which is referred toas a zero error or offset. The u_(par) curve is parallel to u_(ideal)curve. Thus uPAR shows an output voltage of an A/D converter, where thegain error is zero. The u_(real) curve shows the profile of an analog-to-digital converter, the offset error is greater than zero, namely a₀,and the gain error is larger than zero. Using the circuit shown in thefigures, these errors can be determined.

FIG. 3 illustrates an exemplary implementation of a portion of thecircuit 1 illustrated in FIG. 1. As is illustrated, the A/D converter 4is provided in FIG. 3. Furthermore, a detailed implementation of theevaluation circuit 5 is provided in FIG. 3. As was discussed in FIG. 1,the evaluation circuit 5 receives a clock signal CLK at the input C anda digital signal at the input E5. The evaluation circuit 5 include aswitch 51, a control circuit 52, 2 summers 53 and 54, 2 multipliers 58and 57, a memory 591, a memory 59, a divider 60, a divider 601, an adder61, a memory 62, a subtracter 63, a memory 64, a subtracter 65, adivider 66, a memory 67, a multiplier 68 and a memory 69.

The input signal u_(in) is applied to the data input E of the A/Dconverter 4. The rise and fall of the input signal u_(in) is shown inthe graph associated with FIG. 3. As is illustrated, the input signalu_(in) is in a first phase between times t_(a) and t_(b) (u_(steig)).The exponential increase of the input signal u_(in) is at leastassociated with Euler's number. In a further phase, between times t_(c)and t_(d) (u_(fall)), the exponential decrease of the input signal isalso at least associated with Euler's number. The function for u_(steig)is provided by the following formula:

${u_{steig}(t)} = {u_{0}\left( {1 - e^{\frac{- t}{\tau}}} \right)}$The function for u_(fall) is i provided by the following formula:

${u_{fall}(t)} = {u_{0}{e^{\frac{- t}{\tau}}.}}$

The values u₀ and τ are considered to be constants. The value u₀ ischosen such that it is at or within a maximum voltage or voltage rangeof the A/D converter 4.

As should be understood, in various embodiments, the first and furtherphases may be switched. For example, the first phase may be betweentimes t_(c) and t_(d) (u_(fall)) and proceed the further phase betweentimes t_(a) and t_(b) (u_(steig)).

The input of the changeover switch 51 is connected to the output E ofthe A/D converter 4. The control circuit 52 switches the switch 51 sothat the output of the switch 51 is selectively connected to the inputof the summing element 53 and to the input of the summing element 54.The summers 53 and 54 add the value applied to its input to a respectiveregister value, respectively. The timing of the addition can bedetermined in each case by the control circuit 52, this also controls areset, that is, the setting of the register value to zero, if required.

The output of the summing element 53 is connected to a first input ofthe multiplier 58, while the second input of the multiplier 58 isconnected to an output of the memory 591. The output of the summingelement 54 is connected to a first input of the multiplier 57, while thesecond input of the multiplier 57 is connected to the output of thememory 591.

The output of multiplier 58 is connected to a first input of a dividerunit 601, whose second input is connected to the output of the memory59. The divider unit 601 divides the output value of the multiplier 58by the contents of the memory 59, the output of the multiplier 57 isconnected to a first input of divider unit 60, whose second input isconnected to the output of the memory 59. The divider unit 60 dividesthe output of the multiplier 57 by the contents of memory 59.

The output signal of the divider unit 601 and the output of the dividerunit 60 are each connected to an input of the adder 61, which outputsthe sum of the two output signals to the memory 62. This memory 62stores the received value as E.

The output signal of the divider unit 601 and the output of the dividerunit 60 are also respectively connected to one input of the subtracter63, which outputs the difference between the values of the outputsignals to the memory 64. This memory 64 stores the received value as A.

The output of memory 64 is connected to a first input of the multiplier68 whose second input is connected to the output of the memory 69. Theoutput of memory 64 is the one with the output g₀ u₀ and secondlyconnected to the second input of the subtracter 65. The first input ofthe subtractor 65 is connected to the output of the memory 62. Theoutput of subtractor 65 is connected to a first input of a divider unit66, whose second input is connected to an output of the memory 67. Thedividing unit 66 divides the value present at its first input with thevalue present at its second input, and outputs it as a₀.

The adder 61 outputs at its output the sum of the values at its inputs.The multipliers each provide at their outputs the product of the valuesat their inputs. The multipliers 58, 57, 68, the adders 61, the dividerunits 60, 601, 66 and the subtracters 63 and 65 are each designed asdigital circuits. They may each contain one, not shown in the FIG. 3, aclock input that determines the time at which the respective processingoperation is performed. These clock inputs are connected to outputs ofthe control circuit 52, not shown in this FIG. 3.

Alternatively, the multipliers and dividers can be implemented by acentral processing unit. The central processing may be switched in sucha way that in a first time window, the calculations of the units 53, 58and 601 are performed, and the calculations carried out by the units 54,57 and 60 are performed in a second time window.

The embodiment illustrated in the figures, in particular FIG. 3,consider falling considerations.

As input signals, rising and falling exponential functions will be used,taking advantage of the special properties of the exponential functionwith the Euler's number as a base. The rising and falling edge of anexponential function with the amplitude u₀ and the time constant τ aredescribed by the following two relations.

$\begin{matrix}{{u_{{steig},{ideal}}(t)} = {u_{0}\left( {1 - e^{\frac{- t}{\tau}}} \right)}} & {{Formula}\mspace{14mu} 1} \\{{u_{{fall},{ideal}}(t)} = {u_{0}e^{\frac{- t}{\tau}}}} & {{Formula}\mspace{14mu} 2}\end{matrix}$

The time constant τ is the same for both curves. If an A/D converter hasa zero error a0 and a gain error g0, the following voltages of therising edge and the falling edge are provided:

$\begin{matrix}{{u_{steig}(t)} = {a_{0} + {g_{0}{u_{0}\left( {1 - e^{\frac{- t}{\tau}}} \right)}}}} & {{Formula}\mspace{14mu} 3} \\{{u_{fall}(t)} = {a_{0} + {g_{0}u_{0}e^{\frac{- t}{\tau}}}}} & {{Formula}\mspace{14mu} 4}\end{matrix}$

The method is based on the formulation or formation of sums over definedmeasurement interval. The rising and falling values from time t=T0 tot=T0+T1 are given by the following.

$\begin{matrix}{S_{steig} = {\int_{t = T_{0}}^{T_{0} + T_{1}}{{u_{steig}(t)}\ d\; t}}} \\{= {\int_{t = T_{0}}^{T_{0} + T_{1}}{\left( {a_{0} + {g_{0}{u_{0}\left( {1 - e^{\frac{- t}{\tau}}} \right)}}} \right)d\; t}}} \\{= {{\int_{t = T_{0}}^{T_{0} + T_{1}}{\left( {a_{0} + {g_{0}u_{0}}} \right)d\; t}} - {\int_{t = T_{0}}^{T_{0} + T_{1}}{g_{0}{u_{0}\left( e^{\frac{- t}{\tau}} \right)}d\; t}}}} \\{= {{\left( {a_{0} + {g_{0}u_{0}}} \right)\; t}❘_{T_{0}}^{T_{0} + T_{1}}{{{+ g_{0}}u_{0}{\tau\left( e^{\frac{- t}{\tau}} \right)}}❘_{T_{0}}^{T_{0} + T_{1}}}}} \\{= {{\left( {a_{0} + {g_{0}u_{0}}} \right)\; T_{1}} + {g_{0}u_{0}{\tau\left( {e^{\frac{- {({T_{0} + T_{1}})}}{\tau}} - e^{\frac{- T_{0}}{\tau}}} \right)}}}} \\{= {{\left( {a_{0} + {g_{0}u_{0}}} \right)\; T_{1}} - {g_{0}u_{0}{{\tau e}^{\frac{- T_{0}}{\tau}}\left( {1 - e^{\frac{- T_{1}}{\tau}}} \right)}}}}\end{matrix}$ $\begin{matrix}{S_{fall} = {\int_{t = T_{0}}^{T_{0} + T_{1}}{{u_{fall}(t)}\ d\; t}}} \\{= {\int_{t = T_{0}}^{T_{0} + T_{1}}{\left( {a_{0} + {g_{0}u_{0}e^{\frac{- t}{\tau}}}} \right)d\; t}}} \\{= {{\int_{t = T_{0}}^{T_{0} + T_{1}}{a_{0}d\; t}} + {\int_{t = T_{0}}^{T_{0} + T_{1}}{g_{0}{u_{0}\left( e^{\frac{- t}{\tau}} \right)}d\; t}}}} \\{= {{a_{0}t}❘_{T_{0}}^{T_{0} + T_{1}}{{{+ g_{0}}u_{0}{\tau\left( e^{\frac{- t}{\tau}} \right)}}❘_{T_{0}}^{T_{0} + T_{1}}}}} \\{= {{a_{0}T_{1}} - {g_{0}u_{0}{\tau\left( {e^{\frac{- {({T_{0} + T_{1}})}}{\tau}} - e^{\frac{- T_{0}}{\tau}}} \right)}}}} \\{= {{a_{0}T_{1}} + {g_{0}u_{0}{{\tau e}^{\frac{- T_{0}}{\tau}}\left( {1 - e^{\frac{- {(T_{1})}}{\tau}}} \right)}}}}\end{matrix}$

Next, the sum ΣS and the difference ΔS of the two integration resultsare given by following.

∑S = S_(steig) + S_(fall) = (2a₀ + g₀u₀)T₁${\Delta\; S} = {{S_{steig} - S_{fall}} = {{g_{0}u_{0}T_{1}} - {2g_{0}u_{0}\tau\;{e^{\frac{- T_{0}}{\tau}}\left( {1 - e^{\frac{- T_{1}}{\tau}}} \right)}}}}$

T₀ and T₁ can now be selected in this embodiment so that the followingrelations hold:

$T_{1} = {\left. {\tau\;{\ln(2)}}\rightarrow e^{\frac{- T_{1}}{\tau}} \right. = \frac{1}{2}}$$T_{0} = {\left. 0\rightarrow e^{\frac{- T_{0}}{\tau}} \right. = 1}$

Based on the curves in FIG. 3, this means that at the instants to andtc, t each is set to zero, and that tb−ta=td−tc=τ ln (2).

Therefore the following may be provided for ΣS and ΔS as:

$\frac{\Delta\; S}{T_{1}} = {\Delta = {{{g_{0}u_{0}} - {g_{0}u_{0}\frac{1}{\ln\;(2)}}} = {{g_{0}{u_{0}\left( {1 - \frac{1}{\ln\;(2)}} \right)}} \approx {{- 0.4427}g_{0}u_{0}}}}}$${\frac{\sum\; S}{T_{1}} = {\sum{= {{{2a_{0}} + {g_{0}u_{0}}} = {{{2a_{0}} - \frac{\Delta}{0.447}} \approx {{2a_{0}} - {2.259\;\Delta}}}}}}},$where g₀ is a dimensionless number that indicates the gain. When g₀=1 inthe gain error is zero, that is, the gain of the A/D converter is ideal.The product is the gain g₀ u₀ times the swept area of the input signalu_(in). The value a₀ has the dimension of volts and returns thezero-point error.

For desired values, the following are provided:

${{g_{0}u_{0}} \approx {- \frac{\Delta}{0.4427}}} = {{- 2.259}\;\Delta}$$a_{0} \approx \frac{\sum{{+ 2.259}\;\Delta}}{2}$

For a practical implementations, the equations will be mapped to ahardware structure, as shown for example in FIG. 3.

Consequently, the values −2.259 and 2 in are stored the memories 69 and67.

In the example shown, the integration is aided by the summing units 53and 54 and the multipliers 57 and 58. The summers will each receive aregister. In this register, a register content is stored in the form ofa binary number. If the summers receives a rising clock edge at a clockinput, the voltage applied to a data input of the summing value is addedto the register content and saved the result of this addition as the newregister contents. At the end of the measurement, the respectiveregister content is multiplied by one of the multipliers 57 and 58 bythe constant factor TS. The output signal of the multiplier 58corresponds to a first sum and S_(steig) the output of the multiplier 57corresponds to a second sum S_(fall).

The at the clock input of the summing elements 53 and 54 corresponds tothe clock CLK, and hence the sampling rate of the A/D converter 4, thestored value in the memory is equal to the period of the clock CLK.

In further not shown embodiments, the summing elements 53 and 54 areoperated at a higher frequency than the CLK and therefore a value storedin the memory 591 corresponding to T_(s) is smaller than the periodlength of CLK.

In one implementation, the clock inputs of the multipliers 58, 57, 68,adders 61, 65, the divider units 60, 601, 66 and the subtracter 65 aresupplied with a clock having a lower frequency as CLK. In the embodimentshown, the circuits receive a clock signal only once during ameasurement and, in particular in one example, when the first and secondphases are over. For this purpose, a counter is provided in the controlcircuit 52, which counts up to the end of the second phase.

The integrating described herein may be accomplished by way of digitalintegration techniques. That is, an accumulation of products fromrespective signal values and the time interval from the previous signalvalue.

The embodiments shown in the figures, in some embodiments, the timeinterval between two additions is constant in the same as TS. For thisreason, it is possible to initially add all the values to be added insuccession to a register content to subsequently multiply the contentsof register with TS. This can be illustrated with instructions inpseudo-code:

begin { Register Contents: = 0; from (t = T0) to (t ≥ T1 − tclk) Loop{t: = t + tclk; Register Contents: = register contents + out (t);} endloop; result of integration = register contents * tclk; end}out (t) denotes the digital value that is output from the Q output ofthe AD converter, and the tclk period length of the clock CLK.

The single multiplication in the foregoing as compared to a multiplemultiplying has the advantage that little power is consumed becauseusually a multiplication consumes more power than an addition.

In other embodiments, the addition is not carried out periodically atequidistant points in time, but also at non-equidistant times. In thiscase, the respective output of the A/D converter 4 is multiplied by thetime difference to the previous time of calculation. The results of themultiplications are added to one another. The following pseudo-code willillustrate this:

begin { register Contents: = 0; from (t = T0) to (t ≥ T1 TABT) Loop {t:= t + TABT; Register Contents: = register contents + E * TABT;} endloop; resolved of integration = register contents; end}

The TABT refers to the time difference from the preceding sampling time.If the time points are non-equidistant to each other, the followedvaries TABT.

However, the latter method of calculation may be used for bothequidistant points in time as well as non-equidistant consecutive timepoints.

The implementations provided provide the determination of the gain errorand rounding errors. When the values for these parameters aredetermined, these values can include quantization by the analog todigital converter and rounding errors. To minimize these roundingerrors, it can be useful in certain embodiments, for an A/D converter,for example, to select a value other than zero for T0 to start measuringsomething later.

An embodiment of the method can be summarized as follows:

-   -   It will be used for exponential functions with a known amplitude        u₀ and a known time constant τ as stimuli for the A/D converter.    -   The output code of the A/D converter are added up for the rising        and falling edge over specific time periods.    -   From the differences in the sums, the offset error and the gain        error result may be found, and after the subtraction or a        division is carried out by a known factor.

Certain embodiments have the following properties:

-   -   The function values of the exponential function correspond to        the output codes of the tested ADC.    -   The amplitude u₀ corresponds to the number of possible output        codes. In the case of an A/D converter with a resolution of B        bits it is known that u₀=2^(B)*an increment of the A/D        converter.    -   The exponential input signal of the ADC is sampled at a constant        data rate fs and converted into a digital output code.    -   The time interval between two sampled values is equal to        Ts=1/fs.    -   A counter controls the number of the sampled values.    -   The well-known time constant τ corresponds to τ=Nτ*fs pulses.    -   The period of time T1 corresponds NT1=ln (2) τ*fs pulses.    -   NT and NT1 are rounded to whole numbers or sizes.    -   The digital output of the A/D converter is connected to at least        one accumulator, which accumulates the output codes of a certain        number of cycles.    -   The start and the end of the accumulation is controlled by a        control unit.    -   Depending on the count, the flanks and further process        conditions, the summers are switched on and off.    -   A multiplication unit scales the obtained values from the sums        and differences to the final size.

Further exemplary examples have the following properties:

1. The tested A/D converter is fed with the falling and rising edges ofan exponential function.

2. The amplitude of the exponential signals is known.

3. The arrangement comprises at least one register, wherein the A/Dconverter the falling edges of output value of the are accumulated.

4. The arrangement includes at least one register, wherein the A/Dconverter the rising edges of output value of the are accumulated.

5. The arrangement includes a control unit, which controls theprocedure. In particular, the control unit determines whether the dataon the rising or falling edge is to be processed, as well as the pointsin time at which the accumulation begins and ends.

6. The arrangement includes a number of computing units, for formingsums, differences, quotients, and products.

7. The arrangement includes a processor (central processing unit (CPU)),and the least part of the functional aspects of the computing units canbe mapped into the processor in the form of a software program andexecuted by the CPU.

Although various exemplary embodiments of the invention have beendisclosed, it will be apparent to those skilled in the art that variouschanges and modifications can be made which will achieve some of theadvantages of the invention without departing from the spirit and scopeof the invention. It will be obvious to those reasonably skilled in theart that other components performing the same functions may be suitablysubstituted. It should be mentioned that features explained withreference to a specific figure may be combined with features of otherfigures, even in those cases in which this has not explicitly beenmentioned. Further, the methods of the invention may be achieved ineither all software implementations, using the appropriate processorinstructions, or in hybrid implementations that utilize a combination ofhardware logic and software logic to achieve the same results. Suchmodifications to the inventive concept are intended to be covered by theappended claims.

The invention claimed is:
 1. A method of characterizing ananalog-to-digital converter, the analog-to-digital converter configuredto convert an input signal to a digital output signal, the methodcomprising: applying the input signal to the analog-to-digital converterthat in a first phase at least includes a profile of a risingexponential function with Euler's number as the base, and in a furtherphase has a profile of a falling exponential function with Euler'snumber as the base; integrating the digital output signal during thefirst phase to provide a first sum; integrating the digital outputsignal during the further phase to provide a second sum; and calculatingfrom the first sum and the second sum at least one of a gain error ofthe analog-to-digital converter and/or and a zero-point error of theanalog-to-digital converter.
 2. The method according to claim 1, whereinthe rising and falling exponential functions make use of a common timeconstant.
 3. The method according to claim 1, further comprisingscanning the input signal using a constant sampling frequency.
 4. Themethod according to claim 1, wherein the rising exponential function isgiven by ${{u(t)} = {u_{0}*\left( {1 - e^{\frac{- t}{\tau}}} \right)}},$wherein t is time, τ is a time constant, u₀ is a constant, wherein u₀ issmaller than or equal to a size of an input range of theanalog-to-digital converter.
 5. The method according to claim 1, whereinthe falling exponential function is given by u(t)=u₀*e^((−t/τ)), whereint is time, τ is a time constant, u₀ is a constant, wherein u₀ is smallerthan or equal to a size of an input range of the analog-to-digitalconverter.
 6. The method according to claim 1, wherein the first phasehas a time duration of T₁ and the second phase has a time duration ofT₂, T₁=T₂=ln(2)*τ, wherein τ is a time constant of the exponentialfunctions.
 7. The method according to claim 3, wherein the constantsampling frequency is greater than 2^(B)*1/(T₁), where T₁ is a timeduration of the first phase and B is a resolution of theanalog-to-digital converter.
 8. The method according to claim 1, whereincalculating includes determining a difference value from the first sumand the second sum.
 9. An electrical circuit for characterizing ananalog-to-digital converter, the analog-to-digital converter configuredto convert an input signal to a digital output signal, the electricalcircuit comprising: a generator to provide the input signal, the inputsignal in a first phase at least includes a profile of a risingexponential function with Euler's number as the base, and in a furtherphase has a profile of a falling exponential function with Euler'snumber as the base an integrator to integrate the digital output signalduring the first phase 2 to provide a first sum and to integrate thedigital output signal during the further phase to provide a second sum;a calculation unit to calculate from the first sum and the second sum atleast one of a gain error of the analog-to-digital converter and/or anda zero-point error of the analog-to-digital converter.
 10. Theelectrical circuit according to claim 9, wherein the rising and fallingexponential functions make use of a common time constant.
 11. Theelectrical circuit according to claim 9, scanning wherein theanalog-to-digital converter is configured to scan the input signal hasat a constant sampling frequency.
 12. The electrical circuit accordingto claim 9, wherein the rising exponential function is given by${{u(t)} = {u_{0}*\left( {1 - e^{\frac{- t}{\tau}}} \right)}},$ whereint is time, τ is a time constant, u₀ is a constant, wherein u₀ is smallerthan or equal to a size of an input range of the analog-to-digitalconverter.
 13. The electrical circuit according to claim 9, wherein thefalling exponential function is given by u(t)=u₀*e^((−t/τ)), wherein tis time, τ is a time constant, u₀ is a constant, wherein u₀ is smallerthan or equal to a size of an input range of the analog-to-digitalconverter.
 14. The electrical circuit according to claim 9, wherein thefirst phase has a time duration of T₁ and the second phase has a timeduration of T₂, T₁=T₂=ln(2)*τ, wherein τ is a time constant of theexponential functions.
 15. The electrical circuit according to claim 11,wherein the constant sampling frequency is greater than 2^(B)*1/(T₁),where T₁ is a time duration of the first phase and B is a resolution ofthe analog-to-digital converter.
 16. The electrical circuit according toclaim 9, wherein the electrical circuit in the analog-to-digitalconverter are monolithically integrated.
 17. The electrical circuitaccording to claim 9, wherein the calculation unit comprises a summationunit for calculating a sum from the first sum and the second sum and adifference unit for determining a difference between the first sum andthe second sum.